Altera recently announced that it has begun shipping its production-qualified Stratix II GX FPGAs. The high-density Stratix II GX family provides up to 20 low-power transceivers operating between 600 Mbps and 6.375 Gbps with an unprecedented 127 Gbps of aggregate serial link connectivity.

Customers are now using Stratix II GX FPGAs to design and manufacture multi-gigabit-interconnected systems that meet or exceed their performance and signal integrity specifications. Additionally, with the release of the EP2SGX30 and EP2SGX60 devices, Altera has completed the roll out of all Stratix II GX family members.

"The 90-nm Stratix II GX devices provide customers with technology advantages, including the lowest-power transceiver of its type. Additionally, Stratix II GX FPGAs demonstrate excellent signal integrity performance that the devices pass stringent SONET OC48 and STM16 optical jitter tests with margin, while the core of the FPGA and I/O toggle at a high rate," said Louie Leung, Altera Asia Pacific marketing director.

According to a statement from Altera, Stratix II GX devices have been integrated into a wide variety of applications. Many of these customer systems are now transitioning to production, including high-speed backplane and cabling interfaces, chip-to-chip interconnects, and protocol-bridging applications, including, but not limited to, such protocols as PCI Express, CEI-6G, serial digital interface (SDI), Gigabit Ethernet, Serial RapidIO (SRIO), XAUI, SerialLite II, Fibre Channel and SONET/SDH.

Designers are using the Stratix II GX FPGA comprehensive system solution to ease development of high-speed serial applications. The system solution includes Altera Quartus II development software; signal integrity, power distribution and power estimation tools; intellectual property (IP) cores; system models from Altera, Cadence Design Systems, and Mentor Graphics; reference designs; and supporting collateral.

By utilizing this ecosystem, customers can complete their designs in the shortest amount of time and help decrease the cost and risk associated with the challenges of high-speed system integration.